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"High-performance STT-MRAM Logic-in-Memory Scheme Utilizing Data Read Features."

Kai Liu et al. (2022)

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DOI: 10.1145/3565478.3572322

access: closed

type: Conference or Workshop Paper

metadata version: 2023-06-15

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  dblp key:
  - conf/nanoarch/LiuWZ022
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  - https://dblp.org/rec/conf/nanoarch/LiuWZ022
Kai Liu, Bi Wu, Haonan Zhu, Weiqiang Liu:
High-performance STT-MRAM Logic-in-Memory Scheme Utilizing Data Read Features. NANOARCH 2022: 2:1-2:6

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