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"Hardware Design of a 256-Bit Prime Field Multiplier Suitable for Computing ..."

Cuautëmoc Chävez Corona, Edgar Ferrer Moreno, Francisco Rodríguez-Henríquez (2011)

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DOI: 10.1109/RECONFIG.2011.46

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-23

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  - https://dblp.org/rec/conf/reconfig/CoronaMR11
Cuautëmoc Chävez Corona, Edgar Ferrer Moreno, Francisco Rodríguez-Henríquez:
Hardware Design of a 256-Bit Prime Field Multiplier Suitable for Computing Bilinear Pairings. ReConFig 2011: 229-234

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