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ORCID"Scheduling of Iterative Algorithms on FPGA with Pipelined Arithmetic Unit."
Premysl Sucha, Zdenek Pohl, Zdenek Hanzálek (2004)
- Premysl Sucha, Zdenek Pohl, Zdenek Hanzálek:
Scheduling of Iterative Algorithms on FPGA with Pipelined Arithmetic Unit. IEEE Real-Time and Embedded Technology and Applications Symposium 2004: 404-412
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