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"Sizing CMOS circuits by means of the gm/ID methodology and a compact model."

Paul G. A. Jespers (2008)

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DOI: 10.1145/1404371.1404373

access: closed

type: Conference or Workshop Paper

metadata version: 2018-11-06

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  dblp key:
  - conf/sbcci/Jespers08
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Paul G. A. Jespers:
Sizing CMOS circuits by means of the gm/ID methodology and a compact model. SBCCI 2008: 1

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