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"Area and performance optimization of a generic network-on-chip architecture."

Mário P. Véstias, Horácio C. Neto (2006)

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DOI: 10.1145/1150343.1150365

access: closed

type: Conference or Workshop Paper

metadata version: 2018-11-06

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  dblp key:
  - conf/sbcci/VestiasN06
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  - https://dblp.org/rec/conf/sbcci/VestiasN06
Mário P. Véstias, Horácio C. Neto:
Area and performance optimization of a generic network-on-chip architecture. SBCCI 2006: 68-73

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