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ORCID"Difficulty of predicting interconnect delay in a timing driven FPGA CAD flow."
Valavan Manohararajah et al. (2006)
- Valavan Manohararajah, Gordon R. Chiu, Deshanand P. Singh
, Stephen Dean Brown:
Difficulty of predicting interconnect delay in a timing driven FPGA CAD flow. SLIP 2006: 3-8
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