"System-Level Behavioral Model of a 12-Bit 1.5-Bit Per Stage Pipelined ADC ..."

Vicente Yair Ponce-Hinestroza, Victor R. Gonzalez-Diaz (2018)

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DOI: 10.1109/SMACD.2018.8434881

access: closed

type: Conference or Workshop Paper

metadata version: 2021-09-19

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Vicente Yair Ponce-Hinestroza, Victor R. Gonzalez-Diaz:
System-Level Behavioral Model of a 12-Bit 1.5-Bit Per Stage Pipelined ADC Based on Verilog^®=-AMS. SMACD 2018: 301-304

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