"Implementation of a RISC-V SMT Core in an AI processor."

Hidetaro Tanaka et al. (2022)

> Home

Details and statistics

DOI: 10.1145/3568562.3568634

access: closed

type: Conference or Workshop Paper

metadata version: 2022-12-05

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/soict/TanakaTHSTN22
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/soict/TanakaTHSTN22
Hidetaro Tanaka, Tomoaki Tanaka, Ryosuke Higashi, Tsutomu Sekibe, Shuichi Takada, Hironori Nakajo:
Implementation of a RISC-V SMT Core in an AI processor. SoICT 2022: 15-22

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.