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"Implementation of Gating Technique with Modified Scan Flip-Flop for Low ..."

R. Jayagowri, K. S. Gurumurthy (2012)

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DOI: 10.1007/978-3-642-31494-0_7

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-17

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  dblp key:
  - conf/vdat/JayagowriG12
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  - https://dblp.org/rec/conf/vdat/JayagowriG12
R. Jayagowri, K. S. Gurumurthy:
Implementation of Gating Technique with Modified Scan Flip-Flop for Low Power Testing of VLSI Chips. VDAT 2012: 52-58

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