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"Power optimized PLL implementation in 180nm CMOS technology."

Sreehari Rao Patri et al. (2014)

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DOI: 10.1109/ISVDAT.2014.6881065

access: closed

type: Conference or Workshop Paper

metadata version: 2021-05-24

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Sreehari Rao Patri, Pavankumarsharma Devulapalli, Dhananjay Kewale, Omkar Asbe, K. S. R. Krishna Prasad:
Power optimized PLL implementation in 180nm CMOS technology. VDAT 2014: 1-2

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