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"Automatic netlist scrambling methodology in ASIC design flow to hinder the ..."

Sharareh Zamanzadeh, Ali Jahanian (2013)

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DOI: 10.1109/VLSI-SOC.2013.6673245

access: closed

type: Conference or Workshop Paper

metadata version: 2017-12-30

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Sharareh Zamanzadeh, Ali Jahanian:
Automatic netlist scrambling methodology in ASIC design flow to hinder the reverse engineering. VLSI-SoC 2013: 52-53

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