"Catena: A 0.5-V Sub-0.4-mW 16-Core Spatial Array Accelerator for Mobile ..."

Joao Pedro Cerqueira et al. (2019)

> Home

Details and statistics

DOI: 10.23919/VLSIC.2019.8777987

access: closed

type: Conference or Workshop Paper

metadata version: 2019-08-05

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/vlsic/CerqueiraRPPKS19
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/vlsic/CerqueiraRPPKS19
Joao Pedro Cerqueira, Thomas J. Repetti, Yu Pu, Shivam Priyadarshi, Martha A. Kim, Mingoo Seok:
Catena: A 0.5-V Sub-0.4-mW 16-Core Spatial Array Accelerator for Mobile and Embedded Computing. VLSI Circuits 2019: 54-

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.