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"PETRA: A 22nm 6.97TFLOPS/W AIB-Enabled Configurable Matrix and Convolution ..."

Sung-Gun Cho et al. (2021)

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DOI: 10.23919/VLSICIRCUITS52068.2021.9492517

access: closed

type: Conference or Workshop Paper

metadata version: 2022-12-07

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Sung-Gun Cho, Wei Tang, Chester Liu, Zhengya Zhang:
PETRA: A 22nm 6.97TFLOPS/W AIB-Enabled Configurable Matrix and Convolution Accelerator Integrated with an Intel Stratix 10 FPGA. VLSI Circuits 2021: 1-2

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