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"A 14b 750MS/s DAC in 20nm CMOS with <-168dBm/Hz noise floor beyond ..."

Sang Min Lee et al. (2015)

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DOI: 10.1109/VLSIC.2015.7231251

access: closed

type: Conference or Workshop Paper

metadata version: 2023-08-29

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Sang Min Lee, Dongwon Seo, Shahin Mehdizad Taleie, Derui Kong, Michael Joseph McGowan, Tongyu Song, Ganesh R. Saripalli, Jenny Kuo, Seyfi S. Bazarjani:
A 14b 750MS/s DAC in 20nm CMOS with <-168dBm/Hz noise floor beyond Nyquist and 79dBc SFDR utilizing a low glitch-noise hybrid R-2R architecture. VLSIC 2015: 164-

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