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"TWTXBB: A Low Latency, High Throughput Multiplier Architecture Using a New ..."

Debabrata Ghosh, S. K. Nandy, K. Parthasarathy (1994)

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DOI: 10.1109/ICVD.1994.282660

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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  dblp key:
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  - https://dblp.org/rec/conf/vlsid/GhoshNP94
Debabrata Ghosh, S. K. Nandy, K. Parthasarathy:
TWTXBB: A Low Latency, High Throughput Multiplier Architecture Using a New 4 --> 2 Compressor. VLSI Design 1994: 77-82

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