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"An efficient automatic test generation system for path delay faults in ..."

Ananta K. Majhi et al. (1995)

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DOI: 10.1109/ICVD.1995.512097

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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  - conf/vlsid/MajhiJPA95
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Ananta K. Majhi, James Jacob, Lalit M. Patnaik, Vishwani D. Agrawal:
An efficient automatic test generation system for path delay faults in combinational circuits. VLSI Design 1995: 161-165

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