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"Design of 8-bit Dadda Multiplier using Gate Level Approximate 4: 2 Compressor."

Kattekola Naresh, Y. Padma Sai, Shubhankar Majumdar (2022)

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DOI: 10.1109/VLSID2022.2022.00059

access: closed

type: Conference or Workshop Paper

metadata version: 2022-12-07

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  dblp key:
  - conf/vlsid/NareshSM22
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Kattekola Naresh, Y. Padma Sai, Shubhankar Majumdar:
Design of 8-bit Dadda Multiplier using Gate Level Approximate 4: 2 Compressor. VLSID 2022: 269-274

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