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"Amber: A 367 GOPS, 538 GOPS/W 16nm SoC with a Coarse-Grained ..."

Alex Carsello et al. (2022)

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DOI: 10.1109/VLSITECHNOLOGYANDCIR46769.2022.9830509

access: closed

type: Conference or Workshop Paper

metadata version: 2023-09-30

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  dblp key:
  - conf/vlsit/CarselloFKKLMNS22
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  - https://dblp.org/rec/conf/vlsit/CarselloFKKLMNS22
Alex Carsello, Kathleen Feng, Taeyoung Kong, Kalhan Koul, Qiaoyi Liu, Jackson Melchert, Gedeon Nyengele, Maxwell Strange, Keyi Zhang, Ankita Nayak, Jeff Setter, James Thomas, Kavya Sreedhar, Po-Han Chen, Nikhil Bhagdikar, Zachary Myers, Brandon D'Agostino, Pranil Joshi, Stephen Richardson, Rick Bahr, Christopher Torng, Mark Horowitz, Priyanka Raina:
Amber: A 367 GOPS, 538 GOPS/W 16nm SoC with a Coarse-Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra. VLSI Technology and Circuits 2022: 70-71

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