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"Scaling Dual-Gate Ultra-thin a-IGZO FET to 30 nm Channel Length with ..."

Kaifei Chen et al. (2022)

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DOI: 10.1109/VLSITECHNOLOGYANDCIR46769.2022.9830389

access: closed

type: Conference or Workshop Paper

metadata version: 2023-09-30

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  dblp key:
  - conf/vlsit/ChenNYLLLHDLWWL22
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  - https://dblp.org/rec/conf/vlsit/ChenNYLLLHDLWWL22
Kaifei Chen, Jiebin Niu, Guanhua Yang, Menggan Liu, Wendong Lu, Fuxi Liao, Kailiang Huang, XinLv Duan, Congyan Lu, Jiawei Wang, Lingfei Wang, Mengmeng Li, Di Geng, Chao Zhao, Guilei Wang, Nianduan Lu, Ling Li, Ming Liu:
Scaling Dual-Gate Ultra-thin a-IGZO FET to 30 nm Channel Length with Record-high Gm, max of 559 µS/µm at VDS=1 V, Record-low DIBL of 10 mV/V and Nearly Ideal SS of 63 mV/dec. VLSI Technology and Circuits 2022: 298-299

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