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"Low-ESL (<1 pH @ 8.5 GHz) Multi-Terminal Si Capacitor Embedded in 3D ..."

Kyosuke Kobinata et al. (2022)

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DOI: 10.1109/VLSITECHNOLOGYANDCIR46769.2022.9830411

access: closed

type: Conference or Workshop Paper

metadata version: 2022-08-04

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  dblp key:
  - conf/vlsit/KobinataFSMHAIH22
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  - https://dblp.org/rec/conf/vlsit/KobinataFSMHAIH22
Kyosuke Kobinata, Tatsuya Funaki, Yoshiaki Satake, Hitoshi Matsuno, Seiji Hidaka, Shunsuke Abe, Hiroyuki Ito, Chih-Cheng Hsiao, Sheng Yi Li, Young-Suk Kim, Takayuki Ohba:
Low-ESL (<1 pH @ 8.5 GHz) Multi-Terminal Si Capacitor Embedded in 3D Functional Interposer for Power Delivery Network. VLSI Technology and Circuits 2022: 385-386

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