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"A Refinement Calculus for the Synthesis of Verified Hardware Descriptions ..."

Peter T. Breuer et al. (1997)

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DOI: 10.1145/262004.262007

access: closed

type: Journal Article

metadata version: 2020-10-28

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  - https://dblp.org/rec/journals/toplas/BreuerKLMF97
Peter T. Breuer, Carlos Delgado Kloos, Andrés Marín López, Natividad Martínez Madrid, Luis Sánchez Fernández:
A Refinement Calculus for the Synthesis of Verified Hardware Descriptions in VHDL. ACM Trans. Program. Lang. Syst. 19(4): 585-616 (1997)

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