"A Highly Parallel DRAM Architecture to Mitigate Large Access Latency and ..."

Tareq A. Alawneh et al. (2024)

> Home

Details and statistics

DOI: 10.1109/ACCESS.2024.3512176

access: open

type: Journal Article

metadata version: 2025-01-08

- view
  - electronic edition via DOI (open access)
  authority control:
- export record
  dblp key:
  - journals/access/AlawnehSSAAAA24
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/access/AlawnehSSAAAA24
Tareq A. Alawneh, Ahmed A. M. Sharadqh, Ashraf Al Sharah, Emad A. Awada, Jawdat S. Alkasassbeh, Ayman Y. Al-Rawashdeh, Aws Al-Qaisi:
A Highly Parallel DRAM Architecture to Mitigate Large Access Latency and Improve Energy Efficiency of Modern DRAM Systems. IEEE Access 12: 182998-183023 (2024)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.