"Efficient and Scalable Architecture for Multiple-Chip Implementation of ..."

Tomoya Kashimata et al. (2024)

> Home

Details and statistics

DOI: 10.1109/ACCESS.2024.3374089

access: open

type: Journal Article

metadata version: 2024-04-01

- view
  - electronic edition via DOI (open access)
  authority control:
- export record
  dblp key:
  - journals/access/KashimataYHT24
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/access/KashimataYHT24
Tomoya Kashimata, Masaya Yamasaki, Ryo Hidaka, Kosuke Tatsumura:
Efficient and Scalable Architecture for Multiple-Chip Implementation of Simulated Bifurcation Machines. IEEE Access 12: 36606-36621 (2024)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.