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"Design Method of Vertical Lattice Loop Structure for Parasitic Inductance ..."
Si-Seok Yang et al. (2022)
- Si-Seok Yang, Sung-Soo Min
, Chan-Hyeok Eom
, Rae-Young Kim
, Gi-Young Lee
:
Design Method of Vertical Lattice Loop Structure for Parasitic Inductance Reduction in a GaN HEMTs-Based Converter. IEEE Access 10: 117215-117224 (2022)
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