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"An efficient VLSI architecture of speeded-up robust feature extraction for ..."

Weilong Zhang et al. (2013)

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DOI: 10.1007/S11432-013-4786-9

access: closed

type: Journal Article

metadata version: 2020-03-27

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  - journals/chinaf/ZhangLYZCW13
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  - https://dblp.org/rec/journals/chinaf/ZhangLYZCW13
Weilong Zhang, Leibo Liu, Shouyi Yin, Renyan Zhou, Shanshan Cai, Shaojun Wei:
An efficient VLSI architecture of speeded-up robust feature extraction for high resolution and high frame rate video. Sci. China Inf. Sci. 56(7): 1-14 (2013)

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