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"Low power-area designs of 1bit full adder in cadence virtuoso platform."

Karthik Reddy G (2013)

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DOI: —

access: open

type: Informal or Other Publication

metadata version: 2018-08-13

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  - electronic edition @ arxiv.org (open access)
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  dblp key:
  - journals/corr/G13
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  persistent URL:
  - https://dblp.org/rec/journals/corr/G13
Karthik Reddy G:
Low power-area designs of 1bit full adder in cadence virtuoso platform. CoRR abs/1309.2458 (2013)

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