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"FPGA Implementation of High Speed Baugh-Wooley Multiplier using ..."

Ananda Kiran, Navdeep Prashar (2015)

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DOI: —

access: open

type: Informal or Other Publication

metadata version: 2018-08-13

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  - electronic edition @ arxiv.org (open access)
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  dblp key:
  - journals/corr/KiranP15
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  persistent URL:
  - https://dblp.org/rec/journals/corr/KiranP15
Ananda Kiran, Navdeep Prashar:
FPGA Implementation of High Speed Baugh-Wooley Multiplier using Decomposition Logic. CoRR abs/1509.03575 (2015)

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