Stop the war!

Остановите войну!

for scientists:

default search action

combined dblp search
author search
venue search
publication search

ask others

"Mitigating the Latency-Area Tradeoffs for DRAM Design with Coarse-Grained ..."

Chao-Hsuan Huang, Ishan G. Thakkar (2020)

> Home

Details and statistics

DOI: —

access: open

type: Informal or Other Publication

metadata version: 2020-09-15

- view
  - electronic edition @ arxiv.org (open access)
- export record
  dblp key:
  - journals/corr/abs-2008-11367
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/corr/abs-2008-11367
Chao-Hsuan Huang, Ishan G. Thakkar:
Mitigating the Latency-Area Tradeoffs for DRAM Design with Coarse-Grained Monolithic 3D (M3D) Integration. CoRR abs/2008.11367 (2020)

a service of

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.