"High-Speed Area-Efficient Hardware Architecture for the Efficient ..."

Saeideh Nabipour, Javad Javidan (2023)

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DOI: 10.48550/ARXIV.2306.13347

access: open

type: Informal or Other Publication

metadata version: 2023-06-27

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  - journals/corr/abs-2306-13347
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  - https://dblp.org/rec/journals/corr/abs-2306-13347
Saeideh Nabipour, Javad Javidan:
High-Speed Area-Efficient Hardware Architecture for the Efficient Detection of Faults in a Bit-Parallel Multiplier Utilizing the Polynomial Basis of GF(2m). CoRR abs/2306.13347 (2023)

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