"Hardware-Accelerated Event-Graph Neural Networks for Low-Latency ..."

Hiroshi Nakano et al. (2025)

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DOI: 10.48550/ARXIV.2503.06629

access: open

type: Informal or Other Publication

metadata version: 2025-04-11

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  - journals/corr/abs-2503-06629
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  - https://dblp.org/rec/journals/corr/abs-2503-06629
Hiroshi Nakano, Krzysztof Blachut, Kamil Jeziorek, Piotr Wzorek, Manon Dampfhoffer, Thomas Mesquida, Hiroaki Nishi, Tomasz Kryjak, Thomas Dalgaty:
Hardware-Accelerated Event-Graph Neural Networks for Low-Latency Time-Series Classification on SoC FPGA. CoRR abs/2503.06629 (2025)

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