"Reducing Power Dissipation, Delay, and Area in Logic Circuits by Narrowing ..."

Stephen H. Unger (2003)

> Home

Details and statistics

DOI: 10.1109/MDT.2003.1246160

access: closed

type: Journal Article

metadata version: 2020-05-17

- view
  authority control:
- export record
  dblp key:
  - journals/dt/Unger03
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/dt/Unger03
Stephen H. Unger:
Reducing Power Dissipation, Delay, and Area in Logic Circuits by Narrowing Transistors. IEEE Des. Test Comput. 20(6): 18-24 (2003)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.