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"Multi-Clock Latency-Insensitive Architecture and Wrapper Synthesis."

Ankur Agiwal, Montek Singh (2005)

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DOI: 10.1016/J.ENTCS.2005.05.033

access: open

type: Conference or Workshop Paper

metadata version: 2022-12-16

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  - journals/entcs/AgiwalS06
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  - https://dblp.org/rec/journals/entcs/AgiwalS06
Ankur Agiwal, Montek Singh:
Multi-Clock Latency-Insensitive Architecture and Wrapper Synthesis. FMGALS@MEMOCODE 2005: 5-28

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