"A Formalization of a Subset of VHDL in the Boyer-Moore Logic."

David M. Russinoff (1995)

> Home

Details and statistics

DOI: 10.1007/BF01383871

access: closed

type: Journal Article

metadata version: 2020-03-13

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/fmsd/Russinoff95
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/fmsd/Russinoff95
David M. Russinoff:
A Formalization of a Subset of VHDL in the Boyer-Moore Logic. Formal Methods Syst. Des. 7(1/2): 7-25 (1995)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.