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"A Formalization of a Subset of VHDL in the Boyer-Moore Logic."

David M. Russinoff (1995)

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DOI: 10.1007/BF01383871

access: closed

type: Journal Article

metadata version: 2020-03-13

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  - https://dblp.org/rec/journals/fmsd/Russinoff95
David M. Russinoff:
A Formalization of a Subset of VHDL in the Boyer-Moore Logic. Formal Methods Syst. Des. 7(1/2): 7-25 (1995)

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