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"An Adaptive DAC Settling Waiting Time Optimized Ultra Low Voltage ..."

Ryota Sekimoto et al. (2013)

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DOI: 10.1587/TRANSELE.E96.C.820

access: closed

type: Journal Article

metadata version: 2022-12-07

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  - journals/ieicet/SekimotoSYKI13
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  persistent URL:
  - https://dblp.org/rec/journals/ieicet/SekimotoSYKI13
Ryota Sekimoto, Akira Shikata, Kentaro Yoshioka, Tadahiro Kuroda, Hiroki Ishikuro:
An Adaptive DAC Settling Waiting Time Optimized Ultra Low Voltage Asynchronous SAR ADC in 40 nm CMOS. IEICE Trans. Electron. 96-C(6): 820-827 (2013)

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