"A 1.25-Gb/s Digitally-Controlled Dual-Loop Clock and Data Recovery Circuit ..."

Chang-Kyung Seong, Seung-Woo Lee, Woo-Young Choi (2007)

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DOI: 10.1093/IETELE/E90-C.1.165

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type: Journal Article

metadata version: 2020-04-11

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Chang-Kyung Seong, Seung-Woo Lee, Woo-Young Choi:
A 1.25-Gb/s Digitally-Controlled Dual-Loop Clock and Data Recovery Circuit with Enhanced Phase Resolution. IEICE Trans. Electron. 90-C(1): 165-170 (2007)

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