"On-Chip Memory Power-Cut Scheme Suitable for Low Power SoC Platform."

Hiroki Shimano et al. (2009)

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DOI: 10.1587/TRANSELE.E92.C.356

access: closed

type: Journal Article

metadata version: 2023-06-26

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Hiroki Shimano, Fukashi Morishita, Katsumi Dosaka, Kazutami Arimoto:
On-Chip Memory Power-Cut Scheme Suitable for Low Power SoC Platform. IEICE Trans. Electron. 92-C(3): 356-363 (2009)

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