"A VLSI Design of a Pipelining and Area-Efficient Reed-Solomon Decoder."

Wei-min Wang et al. (2007)

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DOI: 10.1093/IETISY/E90-D.8.1301

access: closed

type: Journal Article

metadata version: 2020-04-11

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Wei-min Wang, Du-yan Bi, Xingmin Du, Lin-hua Ma:
A VLSI Design of a Pipelining and Area-Efficient Reed-Solomon Decoder. IEICE Trans. Inf. Syst. 90-D(8): 1301-1303 (2007)

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