"Scan-Out Power Reduction for Logic BIST."

Senling Wang et al. (2013)

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DOI: 10.1587/TRANSINF.E96.D.2012

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type: Journal Article

metadata version: 2020-06-15

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Senling Wang, Yasuo Sato, Seiji Kajihara, Kohei Miyase:
Scan-Out Power Reduction for Logic BIST. IEICE Trans. Inf. Syst. 96-D(9): 2012-2020 (2013)

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