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"Multiple-Bit-Upset and Single-Bit-Upset Resilient 8T SRAM Bitcell Layout ..."
Shusuke Yoshimoto et al. (2012)
- Shusuke Yoshimoto, Takuro Amashita, Shunsuke Okumura, Hiroshi Kawaguchi
, Masahiko Yoshimoto:
Multiple-Bit-Upset and Single-Bit-Upset Resilient 8T SRAM Bitcell Layout with Divided Wordline Structure. IEICE Trans. Electron. 95-C(10): 1675-1681 (2012)
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