"Bit-Error and Soft-Error Resilient 7T/14T SRAM with 150-nm FD-SOI Process."

Shusuke Yoshimoto et al. (2012)

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DOI: 10.1587/TRANSFUN.E95.A.1359

access: closed

type: Journal Article

metadata version: 2024-05-07

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Shusuke Yoshimoto, Takuro Amashita, Shunsuke Okumura, Koji Nii, Masahiko Yoshimoto, Hiroshi Kawaguchi:
Bit-Error and Soft-Error Resilient 7T/14T SRAM with 150-nm FD-SOI Process. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 95-A(8): 1359-1365 (2012)

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