Stop the war!

Остановите войну!

for scientists:

default search action

combined dblp search
author search
venue search
publication search

ask others

"Improved matrix multiplier design for high-speed digital signal processing ..."

Prabir Saha et al. (2014)

> Home

Details and statistics

DOI: 10.1049/IET-CDS.2013.0117

access: closed

type: Journal Article

metadata version: 2023-09-30

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/iet-cds/SahaBBD14
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/iet-cds/SahaBBD14
Prabir Saha, Arindam Banerjee, Partha Bhattacharyya, Anup Dandapat:
Improved matrix multiplier design for high-speed digital signal processing applications. IET Circuits Devices Syst. 8(1): 27-37 (2014)

a service of

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.