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"A synchronous latency-insensitive RISC for better than worst-case design."

Mario R. Casu, Paolo Mantovani (2015)

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DOI: 10.1016/J.VLSI.2014.01.003

access: closed

type: Journal Article

metadata version: 2020-02-20

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Mario R. Casu, Paolo Mantovani:
A synchronous latency-insensitive RISC for better than worst-case design. Integr. 48: 72-82 (2015)

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