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"A 10T SRAM architecture with 40 % enhanced throughput for IMC applications ..."

Ravi S. Siddanath et al. (2024)

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DOI: 10.1016/J.VLSI.2024.102225

access: closed

type: Journal Article

metadata version: 2024-07-11

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  - https://dblp.org/rec/journals/integration/SiddanathGJGK24
Ravi S. Siddanath, Mohit Gupta, Chaitanya Joshi, Manish Goswami, Kavindra Kandpal:
A 10T SRAM architecture with 40 % enhanced throughput for IMC applications benchmarked with CIFAR-10 dataset. Integr. 98: 102225 (2024)

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