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"An Algorithm for Diagnosing Transistor Shorts Using Gate-level Simulation."

Yoshinobu Higami et al. (2009)

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DOI: 10.2197/IPSJTSLDM.2.250

access: closed

type: Journal Article

metadata version: 2020-09-29

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  - https://dblp.org/rec/journals/ipsj/HigamiSTKT09
Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Shin-ya Kobayashi, Yuzo Takamatsu:
An Algorithm for Diagnosing Transistor Shorts Using Gate-level Simulation. IPSJ Trans. Syst. LSI Des. Methodol. 2: 250-262 (2009)

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