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"A network processor architecture for very high speed line interfaces."

Hideyuki Shimonishi, Tutomu Murase (2001)

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DOI: 10.1109/JCN.2001.6596880

access: closed

type: Journal Article

metadata version: 2022-06-23

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Hideyuki Shimonishi, Tutomu Murase:
A network processor architecture for very high speed line interfaces. J. Commun. Networks 3(1): 88-95 (2001)

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