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"Efficient Diminished-1 Modulo (2n+1) Adder Using Parallel Prefix Adder."

Subodh Kumar Singhal et al. (2020)

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DOI: 10.1142/S0218126620501868

access: closed

type: Journal Article

metadata version: 2021-10-14

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  dblp key:
  - journals/jcsc/SinghalMPS20
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  - https://dblp.org/rec/journals/jcsc/SinghalMPS20
Subodh Kumar Singhal, Basant K. Mohanty, Sujit Kumar Patel, Gaurav Saxena:
Efficient Diminished-1 Modulo (2n+1) Adder Using Parallel Prefix Adder. J. Circuits Syst. Comput. 29(12): 2050186:1-2050186:20 (2020)

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