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"Logic Rewiring for Delay and Power Minimization."

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

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Andreas G. Veneris (2004)

Dagstuhl

Trier

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DOI: —

access: closed

type: Journal Article

metadata version: 2021-07-16

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Andreas G. Veneris:
Logic Rewiring for Delay and Power Minimization. J. Inf. Sci. Eng. 20(6): 1231-1238 (2004)

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last updated on 2021-07-16 19:28 CEST by the dblp team

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