"Order-lot pegging for minimizing total tardiness in semiconductor wafer ..."

Jae-Gon Kim, S.-K. Lim (2012)

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DOI: 10.1057/JORS.2011.133

access: closed

type: Journal Article

metadata version: 2020-06-08

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Jae-Gon Kim, S.-K. Lim:
Order-lot pegging for minimizing total tardiness in semiconductor wafer fabrication process. J. Oper. Res. Soc. 63(9): 1258-1270 (2012)

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