"Hardware transactional memory: A high performance parallel programming model."

Chen Fu et al. (2010)

> Home

Details and statistics

DOI: 10.1016/J.SYSARC.2010.06.006

access: closed

type: Journal Article

metadata version: 2020-02-24

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/jsa/FuWWY10
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/jsa/FuWWY10
Chen Fu, Dongxin Wen, Xiaoqun Wang, Xiao-Zong Yang:
Hardware transactional memory: A high performance parallel programming model. J. Syst. Archit. 56(8): 384-391 (2010)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.